`timescale 10ns/1ns
module fsm_seq_test;
reg clk,rst,x;  
wire z;
wire [2:0] state;
fsm_seq u1(rst,clk,x,z,state);
always #10 clk=~clk;
initial
begin
  clk=0;rst=1;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
  #20 rst=0; x=1;
  #20 rst=0; x=1;
  #20 rst=0; x=1;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
  #20 rst=0; x=1;
  #20 rst=0; x=0;
end
initial 
$monitor($time, , ,"clk=%d rst=%d x=%d z=%d",clk,rst,x,z);
endmodule